Utilization of multiple ramp procedures for analog to digital conversion is known (U.S. Pat. Nos. 3,765,012, 4,361,831). However, in spite of all their advantages with regard to high linearity and effective interference suppression, because the input signal does not have to be switched off, easy mains frequency synchronization on account of constant conversion times and, in spite of their high accuracy and a very simple construction which can easily be integrated with the means of semiconductor technology, these procedures have the disadvantage that convergence greatly deteriorates with increasing input signal, see FIG. 1. FIG. 1a shows a block diagram of a prior art analog to digital converter which employs a multiple ramp procedure. The input signal i.sub.e is first up-integrated in a charge summation circuit 1 such as an analog integrator. The output U.sub.a is fed to a threshold comparator 2 which controls logic circuit 4. Logic circuit 4 connects, via analog switches 10 and 11, either of the integrating reference currents 20 or 21 which are of opposite polarity but have the same value, to the input signal. By alternately connecting the reference currents, one during up-integration and the other during down-integration, faster convergence times are achieved without having to switch off the input signal. A microprocessor 9 converts the up-integration time period into a digital value representative of the input signal for further processing or display. Therefore the procedures according to the U.S. Pat. Nos. 3,765,012, 4,361,831 are normally appropriate only up to ratio of approx. 0.3 for input voltage to reference signal. Even with these small ratios, the settle down transient behaviour of the analog to digital converter resulting from the rather weak convergence behaviour, can be disturbing in the case of fast measuring processes. These procedures become completely divergent when the aforementioned ratio becomes greater than 0.5. This means that the resolution must be set with a factor two to three times lower than the actual capabilities of the analog and digital hardware components.
It is the purpose of this invention to specify an analog to digital conversion method in which the advantages of the procedures specified above are retained, while at the same time eliminating their disadvantages consisting of the unfavourable settle down behaviour and restricted resolution, this without unnecessary complications for the construction, i.e. largely retaining the capability of integration in semiconductor technology.